using System;

namespace RapidHDL
{
	/// <summary>
	/// Summary description for Test.
	/// </summary>
	public class Test
	{
		AndGate oAndGate;
		OrGate oOrGate;
		Not oNot;
		NotGate oNotGate;
		RapidHardware oRapidHardware;
		Xor oXor;

		public Test()
		{
			oRapidHardware = new RapidHardware();
			//oAndGate = new AndGate(oRapidHardware.Structure.TopLevelComponent,"and",2);
			//oOrGate = new OrGate(oRapidHardware.Structure.TopLevelComponent,"or",2);
			//oNot = new Not(oRapidHardware.Structure.TopLevelComponent,"not");
			//oNotGate = new NotGate(oRapidHardware.Structure.TopLevelComponent,"not_gate",2);
			oXor = new Xor(oRapidHardware.Structure.TopLevelComponent,"xor");
			oRapidHardware.Structure.GenerateStructure();
		}

		public void DoIt()
		{
			//oRapidHardware.Structure.TestAll("");
			oRapidHardware.InternalLog.DisplayLogs.Add(LogType.VerilogTrace);
			oRapidHardware.InternalLog.EnableDisplayToConsole = true;
			oRapidHardware.Structure.TransformStructure(StructureTransformType.Verilog);

			//oAndGate.BaseTestComponent("");
			//oRapidHardware.Simulation.VerifyComponent( oAndGate);
			//oAndGate.InputNodes[0].NodeState = NodeState.High;
			//oAndGate.InputNodes[1].NodeState = (NodeState)0;
			//oRapidHardware.Simulation.Clock.DoClock(1);
			//System.Windows.Forms.MessageBox.Show(oAndGate.OutputNodes[0].ToString());
		}
	}
}
